1. Field
Embodiments of the present invention generally relate to techniques for designing and manufacturing integrated circuits (ICs). More specifically, embodiments of the present invention relate to a technique for correctly sizing polygons in a mask layout during mask data preparation.
2. Related Art
The dramatic improvements in integrated circuit (IC) integration densities in recent years have largely been made possible by corresponding improvements in semiconductor design and manufacturing technologies.
One such design and manufacturing technology involves sizing (i.e., shrinking/undersizing or growing/oversizing) polygons in an IC mask layout (hereinafter “layout”) during mask data preparation. To change the size of a polygon, each edge in an initial geometry can be displaced at a constant speed to achieve a constant sizing distance. Some application requires that the shape of the resized polygon be substantially similar to the original polygon. For example, this is a requirement when derived layers are generated or an etch bias is applied to an edge.
However, conventional polygon-sizing techniques are often based on heuristics, and when they are used to process certain polygon geometries with large sizing distances, they can modify the shape significantly. For example, when using conventional sizing techniques to downsize a polygon containing a concave vertex associated with an acute angle, the concave vertex can self-intersect on the polygon, which splits the original polygon into two new polygons (referred to as a “split” event). Such a split event changes the original polygon geometry. On the other hand, when these techniques are used to oversize a polygon containing a convex vertex of an acute angle, the acute angle can be projected very far from the original geometry, which also results in an unacceptable change to the shape of the polygon.
Hence, there is a need for a polygon-sizing tool that can be used to resize polygons without the above-described problems.